In complementary bipolar complementary-metal-oxide semiconductor (BiCMOS) fabrication processes, bipolar devices and complementary-metal-oxide-semiconductor (CMOS) devices are integrated on the same semiconductor substrate. High performance bipolar devices, such as NPN and PNP silicon-germanium (SiGe) bipolar transistors, require a high mask count when integrated on the same semiconductor substrate as the CMOS devices. As BiCMOS technology continues to advance in an effort to achieve high performance, such as increased speed, frequency response and gain, and reduced power consumption, semiconductor manufacturers are challenged to provide a complementary BiCMOS process that effectively integrates higher performing bipolar and CMOS devices.
In one approach of complementary BiCMOS process flow, when forming a bipolar device, a buried sub-collector layer is formed below and in contact with a collector region and away from a top surface of a semiconductor substrate. A collector sinker extends from the top surface of the semiconductor substrate down to the buried sub-collector layer. The buried sub-collector layer and the collector sinker may provide an electrical pathway from the collector to a collector contact for external connection. However, the formations of the buried sub-collector layers for the NPN and PNP devices require several implanting steps and masking layers. The formations of the collector sinkers for the NPN and PNP devices also require separate implanting steps and masking layers. These steps in the complementary BiCMOS process flow undesirably add to processing complexity and manufacturing cost. Also, deep trench isolation regions may be required to provide electrical isolation for bipolar devices from other devices, such as CMOS devices, fabricated on the semiconductor substrate. The deep trench isolation regions unavoidably occupy the limited usable space on the semiconductor substrate.
Thus, there is a need in the art for a complementary BiCMOS process for effectively integrating complementary bipolar devices, such as SiGe NPN and PNP devices, with CMOS devices without undesirably increasing processing complexity and manufacturing cost.